Energy-Delay Trade-off in Digital Design

Circuit design will be challenging in the future. Meeting high-speed performance requirement while dissipating low energy cannot be accomplished easily. The ability to identify the energy-delay trade-off during the initial design process allows designers to optimize the overall circuit performance. Using an inverter chain as a representative logic element, this paper investigates the energy-delay trade-off issues associated with transistor sizing, supply voltage scaling and VT adjustment. In addition to these, their combined effects will be studied as well. The paper then concludes with numerous energy-delay trade-off options that can be undertaken in the design process. Introduction As the technology continues to advance, following Moore’s prediction, the smallest feature that can be transferred onto the wafer has spectacularly been reduced over the past years. The number of transistors that can be packed in a single die has therefore increased dramatically. While this scaling trend has brought several advantages in terms of improvement in circuit performance and cost, new challenges are being encountered and brought to the community’s attention in the recent years, many begin to question the possibility of the continuation of this scaling trend. One of the most noticing challenges today is the overheating problem due to the growing power density in a chip. The following plot (Figure 1A) shows the projected IDSAT-VDD product vs. year, by adopting the e ation below as the power measurement benchmark. qu ‚ IDSATäVDD = EstimatedTransistorCountä IDSATäVDD 1 Transistor The curve shown below is generated using the data obtained from ITRS 2003. Aggressiveness of Technology 1.E+04 1.E+05 1.E+06 1.E+07 2002 2004 2006 2008 201